1. Field of the Invention
The present invention relates to a logic circuit which is based on the combination of CMOS and bipolar transistors, and which operates at high speeds consuming reduced amount of electric power. In particular, the invention relates to a logic circuit for integrated circuits employing a fine working of smaller than 0.5 microns and a power source voltage of smaller than 4 volts.
2. Description of the Prior Art
High-speed low-power logic circuits based on the combination of a bipolar and CMOS transistors have recently been drawing great attention as effective means for increasing the operating speed of integrated circuits. A conventional BiCMOS circuit has been discussed in H. Momose et al., IEEE ELECTRON DEVICE MEETING, 1987, pp. 838-840. A two-input NAND circuit using the conventional BiCMOS is shown in FIG. 2. A pertinent device of this kind has been disclosed in Japanese Patent Laid-Open No. 8431/1984 and its circuit diagram is shown in FIG. 9.